1. Field of the Invention
The present invention relates generally to processor-based or microcontroller-based systems, and more particularly, to an apparatus and method of providing a general purpose stack using a processor register set.
2. Description of the Related Art
In processor-based systems, read only memories (ROM) are configured to store information that has been written during the manufacturing process, but which cannot be written to during the normal operating process of the system. Random access memories (RAM) store information that can be directly and randomly read or written. The information stored in ROM is non-volatile (i.e., the information is retained when power is turned off), while that stored in RAM is volatile (i.e., information is lost when power is turned off).
Prior to initialization of the operating system, for example, before the power on self test (POST) has been completed, RAM is neither initialized nor configured. Because of this, use of certain features of RAM, like the stack, is not available. As a result, an application program such as application software and/or firmware, including Basic Input/Output System (BIOS) routines, that is executed during power up or before RAM has been initialized and made accessible, has limited applications. For example, such application software cannot utilize stacks to store variables, build lists, or to implement deeply nested procedures. In addition, as memory technology becomes increasingly complicated, BIOS routines for memory detection and configuration becomes increasingly difficult to implement without availability of stacks.
Accordingly, there is a need in the technology for an apparatus and method for overcoming the aforementioned problems. In particular, there is a need for an apparatus and method for enabling applications to utilize stacks prior to the availability and accessibility of RAM in a processor-based or microcontroller-based system.
A method and apparatus for providing a stack in a processor-based system. In one embodiment, the apparatus comprises a memory for storing instruction sequences by which the processor-based system is processed; and a processor coupled to the memory that executes the stored instruction sequences, where the processor has a plurality of registers. The stored instruction sequences cause the processor to: (a) determine a condition of occupancy of the plurality of registers; and (b) rearrange the contents of each of the plurality of registers in accordance with a predetermined order.